Analysis and Implementation of Modified Feedthrough Logic for High Speed and Low Power StructuresAnalysis and Implementation of Modified Feedthrough Logic for High Speed and Low Power Structures

In this paper, the design of a low power and high performance dynamic circuit using a new CMOS domino logic family called feedthrough logic is presented. The need for faster circuits with low power dissipation has made it common practice to use feedthrough logic. The proposed circuit for low power improves dynamic power consumption as compared to the existing feedthrough logic and improves its speed. The proposed circuit is simulated using 90nm with power supply 0.9 V CMOS process technology from Cadence(R) Virtuoso(R). Exhaustive simulation results in Cadence environment be evidence for that the proposed modified FTL structure has an advantage in reduction of the dynamic power approximately by 55% and accomplish a speed up to 45% on 8-bit ripple carry adder in contrast to existing feedthrough logic.